1. Field
The following description relates to a scheduler and scheduling method for a reconfigurable architecture.
2. Description of Related Art
In general, a reconfigurable architecture is an architecture in which the hardware configuration of a computing device may be changed to optimally perform a task.
When a task is processed only by using hardware, it is difficult to efficiently carry out the task if changes occur in the process. This difficulty arises for hardware that has a fixed configuration. In contrast, if a task is processed only by using software, the task may be carried out in a different manner by reconfiguring the software if changes occur in the process of performing a task. However, the processing speed is slower than when the data is processed directly by hardware. Reconfigurable architecture combines the advantages of both hardware and software to process a task.
As the reconfigurable architecture reduces structural resources and hands over much of optimization process to a compiler, more benefits are obtained related to hardware. For example, requirements for factors such surface area, power, and the like may decrease, but meanwhile the complexity of compiling an algorithm is increased, thereby lengthening the compiling time. In particular, an increase in the compiling time may bring about the loss of flexibility, which may be obtained by use of a reconfigurable processor instead of such hardware logic as an Application Specific Integrated Circuit (ASIC), which may be difficult to reconfigure.